The present invention relates to a semiconductor device and, in particular, relates to a semiconductor including on-chip oscillators.
It is known that the oscillation frequency of an on-chip oscillator serving as a clock signal source in a microcomputer varies with a change in ambient temperature and/or a change in an external power supply voltage.
Although compensating such a variation in the oscillation frequency is performed during a test in a process stage, this compensation is difficult to carry out under all voltage conditions and temperature conditions during a test in the process stage. Moreover, the oscillation frequency changes under the influence of various factors that cannot be foreseen in a test in the process stage. These factors involve a junction leak in a high temperature domain, a rapid rise above threshold in a low temperature domain, a transistor breakdown phenomenon in a high voltage domain, an influence of triode-like operation of transistors in a low voltage domain, etc.
For the above reasons, techniques for compensating a variation in the oscillation frequency due to a temperature change during actual operation are disclosed in patent documents 1 to 4.
For example, patent document 1 discloses the following technique. When CPU 40 is supplied with temperature information from a temperature detector circuit 50, CPU 40 reads control voltage information suitable for the temperature from a storage circuit 60 and supplies this information to a control voltage generator circuit 30. Then, the control voltage generator circuit 30 generates a control voltage based on the control voltage information and a reference clock generator 20 generates a primary reference clock having a desired frequency based on the control voltage. Thereby, it is possible to efficiently acquire a control voltage suitable for ambient temperature at device power-on and to decrease a frequency error attributed to a temperature characteristic of the primary reference clock at device power-on.
Patent document 2 discloses the following technique. A temperature compensated oscillation circuit 10 comprises an oscillator circuit 42 with a piezoelectric vibrator 40; a temperature measuring unit 22 which measures the temperature of the piezoelectric vibrator 40 intermittently and outputs a digital signal corresponding to the measurement result; a counter 28 which takes input of upper bits of the digital signal output from the temperature measuring unit 22, sets the upper bits depending on a least significant bit of the digital signal, and outputs these bits as an address value; a storage unit 30 in which offset values for on/off control of switches provided in capacitor arrays 44 and address values are stored in one-to-one correspondence, wherein an offset value related to an address value which has been input from the counter 28 is read and output from the storage unit 30; and two capacitor arrays 44 provided in the oscillator circuit 42, wherein the capacitance value of each capacitor array is set according to an offset value which has been input from the storage unit 30.
Patent document 3 discloses the following technique. A compensation interval determining circuit 12 evaluates a temperature change based on a detected temperature from a temperature sensor 16 and determines a compensation interval for compensating the oscillation frequency of an oscillator circuit 7 according to the temperature change. A clock signal with a frequency suitable for this compensation interval is selected by a selector circuit 14 and supplied to a compensation control circuit 15. Based on the clock signal, a temperature to digital signal converter circuit 17 converts the temperature detected by the temperature sensor 16 into a digital signal of temperature data. An offset value determining circuit 18 reads an offset value related to the temperature data and the offset value is set in an offset register 19. According to the offset value contained in the offset register 6, switches S1 to Sn are turned on/off and the capacitances of capacitors C1 to Cn are changed in the oscillator circuit 7.
Patent document 4 discloses the following technique. Oscillation cycle data which varies depending on temperature is stored in an EEPROM of a microcomputer and CPU reads data stored in the EEPROM according to a temperature detected by a temperature detector circuit (steps S2, S3). By setting a determined multiplier value in a DPLL circuit (step S4, S5), the oscillation frequency of a multiplied clock signal is compensated.
Furthermore, techniques for compensating a variation in the oscillation frequency due to a change in an external power supply voltage during actual operation are disclosed in patent documents 5 and 6.
Patent document 5 discloses the following technique. An integrated circuit comprising a processor (CPU) and an oscillator (OSC) integrated in a same substrate is provided. The integrated circuit further comprises a data register (R1) into which data can be loaded by the processor. The oscillator functions as a clock source for the processor and the oscillator comprises a capacitor (C) and a current source for charging and discharging the capacitor. By controlling a value of a current for charging and discharging the capacitor, the data register controls an adjustment of the oscillator frequency. The data register is provided in the same substrate of the integrated circuit and data is loaded into it by the processor from an electrically programmable nonvolatile memory (M1) storing frequency correction data.
Patent document 6 discloses the following technique. Within a chip, trimming values are calculated and stored into a nonvolatile memory and trimming data is retrieved, when required, and used to adjust the Vt level of a reference cell and the frequency of an oscillator. Since chip-specific random trimming can be carried out within a chip, control on a per-chip basis is no longer required, even in a case where a plurality of chips are measured by an external device at the same time. Therefore, it is possible to reduce a testing time and man-hours for developing a test program and it is also decrease human errors induced by complicated test programs.